There are several ways to organise memories with respect to the way they are connected to the cache:
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The memory is one word wide and connected via a one word wide bus to the cache(fastest memory).
The memory is more than one word wide (usually four words wide) and connected by an equally wide bus to the low level cache (which is also wide). From the cache multiple busses of one word wide go to a MUX which selects the correct bus to connect to the high level cache.
There are several memory banks which are one word wide, and one word wide bus. There is some logic in the memory that selects the correct bank to use when the memory gets accessed by the cache.
Memory interleaving is a way to distribute individual addresses over memory modules. Its aim is to keep the most of modules busy as computations proceed. With memory interleaving, the low-order k bits of the memory address select a module, and the high-order m bits name a location within that module. Hence, consecutive addresses are located in successive modules. A request to access consecutive memory locations can keep several modules busy at the same time.
There are several banks, which can all be accessed simultaneously by several buses.